Conventionally, for example, in a semiconductor device with a nonvolatile memory such as a flash memory installed therein, various techniques have been proposed so as to ensure data reliability and an anti-tampering characteristic against unfair data alteration and the like to be conducted so as to read out secret information such as electronic certification information and passwords.
The techniques for ensuring the data reliability and anti-tampering characteristic include, for example, an error detection technique in which error detecting codes such as parity codes and checksums are generated based upon each bit structure of data and an error detecting process is carried out by using the error detection codes, and an error detection and correction technique in which error detection and correction codes such as hamming codes are generated and an error detecting process and an error correcting process are carried out by using the error detection and correction codes.
More specifically, in the error detecting technique by using error detection codes, for example, a flash memory is configured so as to have data areas corresponding to a plurality of addresses, each composed of a main data area for storing predetermined data for each address and a redundant data area for storing redundant data used for error detecting processes of the data. In a programming process, an error detection code is generated based upon each of bit structures of programming data, and the programming data is programmed in the main data area, with necessary information being programmed in the redundant data area. Moreover, in a reading process, read-out data is read from the flash memory together with the corresponding redundant data so that, by using the redundant data, an error detecting process for detecting an error of the read-out data is carried out. In the error detection and correction technique by use of the error detection and correction codes, error detection and correction codes are generated based upon the respective bit structures of the programming data in a programming process, and when an error is detected in an error detecting process carried out in a reading process, the error correcting process is carried out.
The error detecting process in the error detecting technique is effectively used, for example, in the case when read-out data from the flash memory is falsely altered by, for example, applying noise to the power supply, so as to detect the alteration of the data and to ensure the anti-tampering characteristic. Moreover, the error correcting process in the error detection and correction process in the error detection and correction technique is effectively used for ensuring the reliability of data since for example, even in the case when data stored in a memory for a long period of time is aged to deteriorate, causing a failure in reading or the like, the data can be corrected.
In the case, upon programming data, on principle, the flash memory writes a value from ‘1’ corresponding to an erased state to ‘0’ corresponding to a programmed state on the bit basis; however, it cannot write a value from ‘0’ corresponding to the programmed state to ‘1’ corresponding to the erased state on the bit basis. More specifically, when the value is to be switched from the programmed state ‘0’ to the erased state ‘1’, an erasing process is carried out; however, the erasing process is carried out through a batch process on a memory block basis composed of, for example, a data area having a predetermined number of addresses. That is, in the erasing process, all the values of bits within a memory block to be erased are erased from ‘0’ to ‘1’, with the result that the value cannot be changed from ‘0’ to ‘1’ on the bit basis.
For this reason, in the case when, for example, data is composed of command data (command codes), once data has been programmed, the erasing process is always executed prior to a programming process for programming the next command code. In contrast, in the case when data is successively changing data, such as program counter data, from the viewpoint of a higher speed in the processing speed, in some cases, a structure is prepared in which the erasing process is not executed for every data programming process, but, after repeating overwriting processes for writing values in the main data area within the data area from ‘1’ to ‘0’ on the bit basis a fixed number of times after the programming process, an erasing process is executed.
In the case of a structure in which redundant data is added for error detection codes, error detection and correction codes and the like, since the error detection codes and the error detection and correction codes are formed in accordance with the bit structure of data stored in the main data area, the redundant data needs to be written when the overwriting process is executed on the main data area on the bit basis. However, as described above, in the flash memory, the writing process from ‘0’ to ‘1’ on the bit basis cannot be carried out; therefore, when an overwriting process is carried out on data, in some cases, it becomes impossible to write redundant data correctly. For this reason, in a conventional semiconductor device provided with a flash memory, it has been impossible to simultaneously provide an error detecting process effective from the viewpoints of data reliability and anti-tampering characteristic and an overwriting process effective from the viewpoint of a high processing speed.
As a technique for simultaneously providing the error detecting process and the overwriting process, for example, an error detecting technique has been proposed in which each of data areas in a flash memory is formed by a main data area, a redundant data area for storing redundant data, and a status area, and, after an erasing process for the entire data area and a programming process of the main data area and the redundant data area have been executed, data that requires no change in the main data area and the redundant data area is programmed in the status area as a so-called overwriting process (for example, see Patent Document 1).
FIG. 11 shows an example of a transition of a value in the data area derived from the error detecting technique described in Patent Document 1. The data area in this case is composed of a 4-bit status area WS, a 4-bit main data area WM and a 4-bit redundant data area WP, and data used for error detection and correction codes relative to an 8-bit area WF composed of the status area WS and the main data area WM is stored in the redundant data area WP.
More specifically, FIG. 11A shows a data area after an erasing process, and all the values of the bits in the data area are set to ‘1’. FIG. 11B shows values in the data area after the first programming process has been executed following the erasing process. In this example of the programming process, a value ‘1010’ is programmed in the main data area WM, and a value ‘1001’ is programmed in the redundant data area WP. As described earlier, the value ‘1001’ programmed in the redundant data area WP forms an error detection and correction code for the value ‘11111010’ of the 8-bit area WF.
FIG. 11C shows values in the data area after a so-called overwriting process (after single-bit alteration). In this so-called overwriting process, a value ‘0001’ is programmed in the status area WS. In this case, the value of the 8-bit area WF becomes ‘00011010’, and the value of the error detection and correction code for this value is set to ‘1001’. Since this value is equal to the value ‘1001’ of the redundant data area WP, it is found that, after the so-called overwriting process, by using the redundant data ‘1001’ stored in the redundant data area WP, an error detecting process can be carried out on the data ‘00011010’ stored in the 8-bit area WF composed of the status area WS and the main data area WM after the so-called overwriting process.    Patent Document 1: Japanese Patent Application National Publication (Laid-Open) No. 2004-524636